Semiconductor Engineering

No-Compromise Packetized Test Improves DFT Efforts

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these ...
Semiconductor Engineering

Power-Aware Test: Addressing Power Challenges In DFT And Test

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design ...
EDN

First STIL link between DFT and production test for SoC

Design-for-test (DFT) software maker Teseda (Portland, Oregon) and test-and-measurement house Agilent Technologies (Palo Alto, Calif.) announce a link that both companies claim will ensure, for the ...
Electronic Design

SoC Test System Speeds Design Verification, Cuts Test Cost

As System-On-A-Chip complexity increases, testing the millions of gates that get integrated on the chip has become an ever more challenging and more expensive task. On-chip test support logic and ...