Semiconductor Engineering

The UVM Configuration Database

When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future. A ...
Semiconductor Engineering

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2 ...
Design-Reuse

Power of UVM's Command Line Argument Usage in Verification Test benches

The growing complexity of ASIC/FPGA designs in recent era has caused simulation times to increase drastically. This is because there is a growing need to ensure that the simulation matches the ...
Design-Reuse

Building Your UVM Verification Environment for Cache Coherent Interconnects

The ARM® AMBA® 4 Coherency Extension (ACE™) specification was officially published more than a year ago. The main driver for the ACE spec is the need to support hardware-managed cache coherency, ...