Semiconductor Engineering

Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s ...
Semiconductor Engineering

Enabling Seamless Monitoring, Test, And Repair In Multi-Die Designs

Anyone who follows the semiconductor industry knows that the accelerating performance, scale and energy efficiency demands of the AI revolution are outpacing the advances achievable by simply pushing ...
EDN

Chiplets: 8 best practices for engineering multi-die designs

Semiconductor design is in the midst of a structural shift. For decades, performance gains were achieved by packing more transistors into single, monolithic dies. But the physical limitations of these ...
Electronic Design

UCIe 3.0: Scaling Multi-Die Designs to the Next Level

What has changed between UCIe 2.0 and UCIe 3.0? Why UCIe matters for enabling next-generation chiplet architectures. Where the semiconductor industry goes next in its chiplet ambitions. The Universal ...
EDN

Chiplet basics: Separating hype from reality

There’s currently a significant buzz within the semiconductor industry around chiplets, bare silicon dies intended to be combined with others into a single packaged device. Companies are beginning to ...
Nasdaq

Arteris Accelerates AI-Driven Silicon Innovation with Expanded Multi-Die Solution

CAMPBELL, Calif., June 17, 2025 (GLOBE NEWSWIRE) -- In a market reshaped by the compute demands of AI, Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP for accelerating semiconductor ...
Electronic Design

Achieving reliable 3D ICs with die-level stress analysis

The rapid adoption of 3D integrated circuits (ICs) and heterogeneous packaging heralds a new era in semiconductor design. Benefits are clear: greater functional density, reduced footprint, and ...